`timescale 1ns/1ps
//in wrapper ,all control signals active high

module rf_2p_d32_w48_wrapper (clk,wren,waddr,wdata,rden,raddr,rdata,rf_2p_cfg_register);
  input  clk;
  input  [6:0] rf_2p_cfg_register;
  input  wren;//write enable,active high 
  input [4:0] waddr;//waddr
  input [47:0] wdata;//wdata
  input  rden;//read enable,active high
  input [4:0] raddr;//raddr
  output [47:0] rdata;//rdata

rf_2p_d32_w48 U_rf_2p_d32_w48(
.QA(rdata), 
.CLKA(clk), 
.CENA(~rden),//read enable,active low 
.CENB(~wren),//write enable,active low
.AA(raddr),
.CLKB(clk), 
.AB(waddr), 
.DB(wdata),  
.EMAA(rf_2p_cfg_register[6:4]), 
.EMASA(rf_2p_cfg_register[3]), 
.EMAB(rf_2p_cfg_register[2:0]),  
.COLLDISN(1'b1), 
.RET1N(1'b1)
);

endmodule
